A read only memory (ROM) is a semiconductor memory which has permanently stored information that can be read, but not erased or rewritten. In most applications, the information stored in the ROM is written into the memory during manufacture of the ROM memory device. FIG. 1 is a cross-sectional view of a conventional ROM semiconductor device in the x-z plane. The device shown has a first cell 1 adapted to store a "1" and a second cell 2 adapted to store a "0". Each cell contains a drain region having a heavily doped portion 4 and a lightly doped portion 6, a gate electrode 8, and a source region having a heavily doped portion 10 and a lightly doped portion 12. Cells 1 and 2 are separated from each other by field oxide region 16. Gate 8 of each cell is insulated from source 10 and drain 6 by oxide layers 17, 18 and 19 as shown.
In cell 2, the thickness of oxide layer 19 underneath gate 8 is significantly less than the thickness of the oxide layer 17 underneath gate 8 of cell 1. This difference represents the information content of the cell. When an appropriate positive voltage is applied to gate 8 of cell 2, an electric field of sufficient magnitude is generated to create a temporary N type channel (not shown) between regions 6 and 10. Current then flows through the transistor device of cell 2 when a voltage is applied at gate 8. The transistor of cell 2 is in the "on" or active state and the cell registers a "0".
When the voltage applied to gate 8 of cell 2 is applied to gate 8 of cell 1, the greater thickness of oxide layer 17 prevents formation of an electric field strong enough to allow current to pass from drain to source. The transistor of cell 1 thus does not turn "on" when this voltage is applied to its gate 8. Cell 1 is in an inactive state and reads a "1". Of course, the "0" and "1" are simply conventions. Off cells can be considered as "0" cells, and on cells as "1" cells.
The structure of the conventional ROM cell 2, however, is subject to electrical breakdown of the gate oxide: a phenomenon known as gate oxide rupture. Unfortunately, during plasma etching to define the polycrystalline silicon (polysilicon) gate regions 8 on the wafer surface, or during ion implantation, the polysilicon gate regions can retain charge. A voltage thus develops between the polysilicon gate region 8 and the underlying substrate. The magnitude of the voltage is a function of the oxide thickness. For a unit area of oxide, the voltage between the polysilicon gate region and the substrate increases as the oxide thickness increases. Conversely, the voltage between the substrate and the polysilicon gate region decreases as the oxide thickness decreases.
FIG. 2 shows a cross section of the gate region of cell 2 in the y-z plane. For the reasons discussed above, in ROM cell 2, gate oxide rupture occurs and ROM cell 2 does not function properly. The voltage on the gate oxide is given by ##EQU1## Where: Q=Charge per unit area
A=Area PA1 C=Capacitance per unit area PA1 g=gate PA1 f=field oxide
This equation can be rewritten as: ##EQU2## by noting that the unit capacitance can be expressed as: ##EQU3## where: .epsilon..sub.ox =oxide dielectric constant and t=the oxide thickness. Gate oxide rupture occurs when V/t.sub.g &gt;10V/100.ANG.. Therefore from equation (2) above, rupture is most likely to occur if A.sub.f /A.sub.g is large when t.sub.g /t.sub.f is small, or approximately 1/30. Thus, in the diagram of FIG. 2 rupture occurs when the ratio of the areas of regions 18 and 19 is large while the ratio of thicknesses of region 19 to region 18 is small.
In prior art ROM devices the field oxide thickness was about 6000.ANG. and the gate oxide thickness was about 800.ANG., or a ratio of 7.5 to 1. At this ratio, the potential differences are such that gate oxide rupture is a relatively infrequent phenomenon. Technological advances in integrated circuit fabrication technology, however, have greatly improved device densities by scaling feature sizes in the z direction (as well as x and y directions). As a result, the thickness ratio between the field oxide region and the gate oxide region has been significantly altered. Newer devices may have ratios of field oxide thickness to gate oxide thickness of 6000.ANG. to 200.ANG., or 30 to 1. For newer devices, with a polysilicon geometry mostly over field oxide and its small remaining area over gate oxide, the rupture of this gate oxide is much more likely to occur than in older, larger devices.